1. Field of the Invention
The present invention generally relates to flip-flop circuits, and more particularly, the present invention relates to a flip-flop circuit which is capable of reducing the load of a clock signal line.
A claim of priority under 35 U.S.C. §119 is made to Korean Patent Application 2002-49890 filed on Aug. 22, 2002, the entire contents of which is hereby incorporated by reference.
2. Description of the Related Art
A conventional flip-flop circuit includes a master latch and a slave latch. Input data are delivered to each latch through transmission gates controlled by clock signals. The master latch and the slave latch have respective feed-back circuits, whereby a current data latched in the flip-flop circuit is maintained until a new data synchronized with the clock signal is input to the flip-flop circuit, and a feed-back status of the flip-flop circuit is controlled by the clock signal.
FIG. 1 schematically illustrates a conventional flip-flop circuit, and FIG. 2 illustrates in greater detail the flip-flop circuit shown in FIG. 1. Referring first to FIG. 1, the conventional flip-flop circuit includes a master latch gate 10, a master latch 20, a slave latch gate 30 and a slave latch 40, each being controlled by an external clock signal CLK. Input data D is inverted by an inverter INV1 and applied to the master latch 10, and output data Q is obtained from the inverter INV2 which inverts the output of the slave latch 40.
As shown in FIG. 2, the external clock signal CLK is passed through inverter INV3 to obtain an inverted internal clock signal CKN, and is further passed through inverter INV4 to obtain an internal clock signal CK. The master latch 10 includes a transmission gate TG1 which is controlled by the clock signals CKN and CK. The master latch 20 includes inverter INV6 connected in parallel with inverter INV7 and transmission gate TG2, where the transmission gate TG2 is controlled by the clock signals CKN and CK. The slave latch gate 30 includes a transmission gate TG3 which is controlled by the clock signals CKN and CK. The slave latch 40 includes inverter INV8 connected in parallel with inverter INV9 and transmission gate TG4, where the transmission gate TG4 is controlled by the clock signals CKN and CK.
As shown, the master latch gate 10, the master latch 20, the slave latch gate 30, and the slave latch 40, all have transmission gates which are controlled by the external clock signal CLK. As a consequence, one significant drawback of this conventional flip-flop circuit resides in the substantial load applied to the clock signal line. The high load of the clock signal line results in an increase in the transition time of the clock signal, which in turn creates a roadblock to achieving high operating speeds.